1. Field of the Invention
The present invention relates to an inter-computer network system wherein a plurality of computers parallelly execute processing of individual jobs thereof while communicating with each other and an inter-computer data transfer method for a computer system.
2. Description of the Related Art
As a result of popularization of system area networks, distributed computing systems have been and are increasing wherein a plurality of computers are connected to each other by a high speed network and parallelly execute processing of individual jobs thereof while communicating with each other.
The parallel processing by a plurality of computers makes it possible to execute a large scale arithmetic operation process which cannot be implemented by a single computer. Also the High Performance Fortran (HPF) which is a standard program language for programming or the Message Passing Interface (MPI) which is a library where a plurality of computers perform arithmetic operation while communicating with each other has been developed, and the parallel processing is used in a progressively increasing wide region and computers having the function are increasing.
Where a plurality of computers are connected to each other by a network and execute parallel processing through mutual communication, at least an arithmetic operation process of performing an actual arithmetic operation and a communication process of performing communication with another computer are required.
When a communication process is performed, if a processor performs the communication process, then the arithmetic operation capacity of the processor is deteriorated by the communication process. In order to use the arithmetic operation capacity of the processor for the arithmetic operation as much as possible, a communication device is sometimes incorporated while removing the communication process from the processor.
The communication device processes a communication instruction from the processor and transfers data of a sending source designated by the communication instruction to a destination designated by the communication instruction. The communication instruction usually designates a sending source address which is an address on a main storage of sending source data, a transfer length which is a length of the data to be transferred and a computer of the sending destination.
The designations of the sending source address, transfer length and sending destination computer in the communication instruction are called Send command. In addition, the designation of a sending destination address which is a main storage address of the sending destination is called Remote DMA Write command.
If the address on the main storage designated by the communication instruction is a physical address, then a process of forwarding the communication instruction to the communication processing apparatus is limited to a privileged process to which a physical address can be known. When a user level process which is a non-privileged process performs a communication process, it issues a request for communication to a privileged process, and the privileged process executes a process of converting a logical address into a physical address by proxy through a process switch. Since such a process switch process as just described requires a very long period of time as viewed from the user process, the process switch process makes one of factors of performance degradation.
In order to prevent the performance degradation by the process switch process described above, the communication device incorporates an address conversion mechanism for converting a logical address into a physical address so that the user process can issue a communication instruction to the communication device without intervention of a privileged process. This is called user level communication and is implemented by a network apparatus for which communication of a high performance with a low latency is required.
When the address conversion mechanism is incorporated, a method is adopted wherein an address conversion table is fully incorporated in the communication device. However, where the address conversion table cannot be incorporated in the communication device, another method is adopted wherein the address conversion table is incorporated in a memory outside the communication device and part of the address conversion table is incorporated as a translation look aside buffer (TLB) in the communication device.
Usually, the following three methods are available to incorporate a TLB:                (1) Full associative method wherein a conversion object logical address is used for comparison of part of logical addresses of all TLB entries and a TLB entry which exhibits coincidence is used for address conversion;        (2) Direct map method wherein some of bits of a conversion object logical address are used as an address of a TLB entry to be used for conversion; and        (3) Set associative method wherein a set of some TLB entries are selected from among all TLBs using some of bits of a conversion object logical address and the logical addresses in all of the TLB entries in the selected set and the conversion object logical address are compared with each other.        
In all of the methods described, a conversion object logical address is used for determination of a TLB entry.
Where a method wherein a TLB is incorporated is adopted, the hit ratio of the TLB has a significant influence on the transfer performance. Therefore, it is expected to raise the hit ratio of the TLB incorporated in the communication device.
A communication device which performs address conversion is disclosed, for example, in Japanese Patent Laid-Open NO. 89056/1993 (hereinafter referred to as Patent Document 1), Japanese Patent Laid-Open No. 262146/1995 (hereinafter referred to as Patent Document 2) and Japanese Patent No. 3,237,599 (hereinafter referred to as Patent Document 3). Patent Document 1 discloses an apparatus wherein a shared memory which performs address conversion is accessed through communication control.
Patent Document 2 discloses another apparatus wherein address conversion is performed by a router and inter-processor communication is performed using a packet. Patent Document 3 discloses a further apparatus wherein address conversion is performed in a processor.
As described hereinabove, where a communication device according to the TLB method is incorporated in a computer in order to implement parallel processing using a plurality of computers, improvement of the hit ratio of a TLB is a significant subject.
As described above, in order to incorporate a TLB in a communication device, usually the direct map method, set associative method or full associative method is used wherein a logical address of an object of conversion and logical addresses in TLB entries are compared with each other.
According to the three methods, a TLB entry to be used for conversion is determined based on a conversion object logical address. Further, since the number of TLB entries is smaller than the size of the address conversion table, replacement of a TLB entry is performed when a miss occurs with the TLB and besides the TLB does not include a free entry.
Since the logical addresses used by a processor have a high locality and exhibit such a behavior that there is a high degree of possibility that a logical address used recently may be used again, the Least Recently Used algorithm (LRU), that is, an algorithm which replaces a TLB which has been least used recently is used frequently as an algorithm for the replacement.
In data transfer, however, the write object address in most cases increases monotonously, and the main storage address indicates a behavior much different from the behavior in accessing of the processor that the possibility that a main storage address used in the past may be re-utilized is low. Therefore, there is a first problem that, if the LRU is used as the replacement algorithm for a TLB entry, then the TLB hit ratio is dropped thereby.
Further, since a TLB held by a reception section of a communication device is used for communication with a plurality of opposite parties, if a TLB entry which is used only with a logical address is used, then all of the TLB entries of the reception section of the communication device are used in response to data transfer from a transmission apparatus of one opposite party of communication and replace those TLB entries which have been used by data communication of transmission apparatus of other opposite parties of communication. Therefore, there is a second problem that the TLB hit ratio is dropped thereby.